Introduction The purpose of this tutorial is to describe the modeling language VHDL. VHDL in-
cludes facilities for describing
logical structure and functi
on of digital systems at a
number of levels of abstraction,
from system level down to the gate level. It is intend-
ed, among other things, as a modeling langua
ge for specification and simulation. We
can also use it for hardware
synthesis if we restrict ourselves to a subset that can be
automatically translated into hardware.
VHDL arose out of the United States
government’s Very High Speed Integrated
Circuits (VHSIC) program. In
the course of this program, it became clear that there
was a need for a standard language for describing the structure and function of inte-
grated circuits (ICs). Hence the VHSI
C Hardware Description Language (VHDL) was
developed. It was subsequently developed
further under the auspices of the Institute
of Electrical and Electronic Engineers (IEEE)
and adopted in the form of the IEEE Standard 1076,
Standard VHDL Language Reference Manual,
in 1987. This first standard
version of the language is often referred to as VHDL-87.
Like all IEEE standards, the VHDL standard
is subject to review at least every five
years. Comments and suggestions from users of the 1987 standard were analyzed by
the IEEE working group responsible for VHDL
, and in 1992 a revised version of the
standard was proposed. This was eventually
adopted in 1993, giving us VHDL-93. A
further round of revision of the standard wa
s started in 1998. That process was com-
pleted in 2001, giving us the curren
t version of the language, VHDL-2002.
This tutorial describes language features
that are common to all versions of the
language. They are expressed using the sy
ntax of VHDL-93 and subsequent versions.
There are some aspects of syntax that are
incompatible with the original VHDL-87 ver-
sion. However, most tools now support at
least VHDL-93, so syntactic differences
should not cause problems.
The tutorial does not comprehensively cover
the language. Instead, it introduces
the basic language features that are needed
to get started in modeling relatively simple
digital systems. For a full cover
age, the reader is referred to
The Designer’s Guide to
VHDL, 2nd Edition
, by Peter J. Ashenden, published by Morgan Kaufman Publishers
(ISBN 1-55860-674-2).
Fundamental Concepts 2.1
Modeling Digital Systems
The term digital systems encompasses a ra
nge of systems from low-level components
to complete system-on-a-chip and board-leve
l designs. If we are to encompass this
range of views of digital systems, we must recognize the complexity with which we
are dealing. It is not humanly possible to comprehend such complex systems in their
entirety. We need to find methods of de
aling with the complexity, so that we can,
with some degree of confidence, design components and systems that meet their re-
quirements.
The most important way of meeting this ch
allenge is to adopt a systematic meth-
odology of design. If we start with a re
quirements document for the system, we can
design an abstract structure that meets
the requirements. We can then decompose
this structure into a collecti
on of components that interact to perform the same func-
tion. Each of these components can in turn be decomposed until we get to a level
where we have some ready-made, primitive components that perform a required
function. The result of this process is
a hierarchically composed system, built from
the primitive elements.
The advantage of this methodology is that
each subsystem can be designed inde-
pendently of others. When we use a subsyste
m, we can think of it as an abstraction
rather than having to consider its detailed
composition. So at
any particular stage in
the design process, we only
need to pay attention to the small amount of information
relevant to the current focus of design. We are saved from being overwhelmed by
masses of detail.
We use the term
model
to mean our understanding of a system. The model rep-
resents that information which is relevant
and abstracts away from
irrelevant detail.
The implication of this is that there may be
several models of the same system, since
different information is relevant in differe
nt contexts. One kind of model might con-
centrate on representing the function of
the system, whereas another kind might rep-
resent the way in which the syst
em is composed of subsystems.
There are a number of important motivations for formalizing this idea of a model,
including
• expressing system requirements in a complete and unambiguous way
• documenting the functionality of a system
• testing a design to verify
that it performs correctly
4
Fundamental Concepts
• formally verifying properties of a design
• synthesizing an implementation in a ta
rget technology (e.g., ASIC or FPGA)
The unifying factor is that we want to achieve maximum reliability in the design
process for minimum cost and design time.
We need to ensure that requirements are
clearly specified and
understood, that subsystems are us
ed correctly and that designs
meet the requirements. A majo
r contributor to excessive co
st is having to revise a
design after manufacture to co
rrect errors. By avoiding e
rrors, and by providing better
tools for the design process, co
sts and delays can be contained.
2.2
VHDL Modeling Concepts
In this section, we look at the basic VHDL
concepts for behavior
al and structural mod-
eling. This will provide a feel for VHDL and a basis from which to work in later chap-
ters. As an example, we look at ways
of describing a four-bit register, shown in
Figure 2-1.
Using VHDL terminology,
we call the module
reg4
a design
entity,
and the inputs
and outputs are
ports
. Figure 2-2 shows a VHDL description of the interface to this
entity. This is an example of an
entity declaration
. It introduces a name for the entity
and lists the input and output po
rts, specifying that they carry bit values (‘0’ or ‘1’) into
and out of the entity. From this we see that
an entity declaratio
n describes the external
view of the entity.